6850ControlRegister
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[edit] 6850 control register
[edit] writing the control register
- bit7
- 1=recv irq enable
- bit6,5 - rts control
- 00 = low, xdata-empty-irq disabled
- 01 = low, xdata-empty-irq enabled
- 10 = high, xdata-empty-irq disabled
- 11 = low, break, xdata-empty-irq disabled
- bit4,3,2 - framing format
- 000 = 7E2
- 001 = 7O2
- 010 = 7E1
- 011 = 7O1
- 100 = 8N2
- 101 = 8N1
- 110 = 8E1
- 111 = 8O1
- bit1,0 - divisor
- 00 = div by 1
- 01 = div by 16
- 10 = div by 64
- 11 = master reset
[edit] reading the control register
- bit7
- interrupt request
- bit6
- parity error
- bit5
- receiver overrun
- bit4
- framing error
- bit3
- clear to send
- bit2
- data carrier detect
- bit1
- txdata register empty
- bit0
- rxdata register full